Electronic Design

32-Bit Architecture Challenges 8-Bit Processors

Can developers utilize a 32-bit architecture with a clear upgrade path even when low power and compact size are high on the list of requirements? Arm Ltd. attempts to answer that question with its ...
Business Wire

Imperas Delivers First RISC-V Simulator for New Vector and Bit Manipulation Specifications to Lead Customers

OXFORD, England--(BUSINESS WIRE)--Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the delivery of its updated simulator for the RISC-V ...
EDN

Building a 4-Bit Computer: Instruction Trade-offs

If you are limiting yourself to only 16 instructions, which ones should you chose, and how do you manage without the ones that fall by the wayside? In my previous column on our project to build a ...
EDN

EDN Access — 09.15.94 EDN’s 21st Annual Microprocessor Directory – 16-bit chip

Special instructions for the H8/500 include load/store multiple regs, link/unlink for building user stack frames, and test and skip. The H8/300, 300L, and 300H have a 14-bit manipulation instruction ...
Design-Reuse

Extending RISC-V ISA With a Custom Instruction Set Extension

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...
Design-Reuse

Creating Domain Specific Processors Using Custom RISC-V ISA Instructions

When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores ...